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| - 1 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 512mbit gddr3 sdram revision 1.0 march 2005 samsung electronics reserves the right to change products or specification without notice. information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for us e in life support, critical care, m edical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any government al procurement to which special terms or provisions may apply.
- 2 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b revision history revision 1.0 (march 8, 2005) ? removed -bc10/11/12 from the spec. ? separated vdd spec as below - vdd & vddq = 2.0v + 0.1v distinguished by part number as -b j - vdd & vddq = 1.8v + 0.1v distinguished by part number as -b c accordingly, defined -bj12/14 and -bc14/16/20 along with supported operating voltage. ? changed trcdr and trp of -bc16 from 9tck and 8tck to 10tck and 9tck. accordingly, trcdw/trc/tdal changed each from 5tck/ 27tck/17tck to 6tck/28tck/18tck. ? changed trcdr and trp of -bc20 from 7tck and 6tck to 8tck and 7tck. accordingly, trcdw/trc/tdal c hanged each from 4tck/ 21tck/13tck to 5tck/22tck/14tck. ? added vendor id read timing on page 18 & clock frequency change timing on page 19. ? changed package dimension from 12mm x 14mm to 11mm x 14mm. ? dc spec updated. ? capacitance values changed. i nput(clock,address,command) capacitance changed fr om 2.0pf/2.5pf to 1.5pf/3.0pf and dq,dqs and dm capacitance changed from 2.0pf/2.5pf to 1.5pf/2.0pf. - 3 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b revision history revision 0.9 (november 11, 2004) ? corrected typo in boundary scan order table. revision 0.8 (october 10, 2004) ? changed part number from k4j52324q b-g to k4j52324q c-b -package code attribute re-defined : g .... 144fbga, leaded v .... 144fbga, lead-free a .... 136fbga, leaded b .... 136fbga, lead-free revision 0.7 (october 5, 2004) ? dc spec defined. ? comment added on how to change the clock frequency after the power-up (page 14) ? comment added on read to write timing diagram on page 32 which sp ecify the timing interval from data termination enable to th e first data-in should be greater than 1tck. ? changed cl(cas latency) of -gc14 from 9tck to 10tck . changed cl(cas latency) of -gc16 from 8tck to 9tck ? typo corrected in boundary scan order table and additional remark for boundary scan added on page 17. ? changed tdcerr from 0.2tck to 0.03tck (typo) revision 0.6 (september 15, 2004) ? typo corrected ? removed twr_a to avoid confusion. inst ead, twr represent write recovery time fo r both normal precharge and auto-precharge cas es. accordingly tdal adjusted by twr for each frequency. ? clock jitter spec added. ? changed input capacitance. ? fixed cl of -gc12 to 11tck where as s pecified with 10tck or 11tck previousely . revision 0.5 (june 4, 2004) ? typo corrected (package ball out) revision 0.4 (may 13, 2004) ? changed trrd from 12ns to 10ns ? added tfaw specification in the spec which defined as five times of trrd ? added boundary scan specification & added package dimension revision 0.3 (january 26, 2004) ? changed part number of 512mb(x32) gddr 3 from k4j53324qb-gc to k4j52324qb-gc revision 0.2 (january 5, 2004) ? added write latency 5, 6, and 7 (clock) in the spec. ? added twr_a 8 and 9 (clock) in the spec. revision 0.1 (december 18, 2003) ? changed cl of -gc12 from 9tck to 10tck ? changed tck(max) from 3.0ns to 3.3ns revision 0.0 (december 18 , 2003) - target spec - 4 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b ? 2.0v + 0.1v power supply for device operation for -bj** ? 2.0v + 0.1v power supply for i/o interface for -bj** ? 1.8v + 0.1v power supply for device operation for -bc** ? 1.8v + 0.1v power supply for i/o interface for -bc** ? on-die termi nation (odt) ? output driver strength adjustment by emrs ? calibrated output drive ? 1.8v pseudo open drain compatible inputs/outputs ? 4 internal banks for concurrent operation ? differential clock inputs (ck and ck ) ? commands entered on each positive ck edge ? cas latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock) ? additive latency (al): 0 and 1 (clock) ? programmable burst length : 4 and 8 ? programmable write latency : 1, 2, 3, 4, 5, 6 and 7 (clock) general description features ? single ended read strobe (rdqs) per byte ? single ended write strobe (wdqs) per byte ? rdqs edge-aligned with data for reads ? wdqs center-aligned with data for writes ? data mask(dm) for masking write data ? auto & self refresh modes ? auto precharge option ? 32ms, auto refresh (8k cycle) ? 136 ball fbga ? maximum clock frequency up to 800mhz ? maximum data rate up to 1.6gbps/pin ? dll for outputs ? boundary scan function with sen pin ? mirror function with mf pin 2m x 32bit x 8 ba nks graphic double data rate 3 synchronous dram with uni-directional data strobe ordering information * K4J52324QC-a*** is lead ed package part number part no. max freq. max data rate vdd&vddq package K4J52324QC-bj12 800mhz 1.6gbps/pin 2.0v+ 0.1v 136 ball fbga K4J52324QC-bj14 700mhz 1.4gbps/pin K4J52324QC-bc14 700mhz 1.4gbps/pin 1.8v+ 0.1v K4J52324QC-bc16 600mhz 1.2gbps/pin K4J52324QC-bc20 500mhz 1.0gbps/pin the K4J52324QC is 536,870,912 bits of hyper synchronous data rate dynamic ram organized as 8 x 2,097,152 words by 32 bits, fabricated with samsung ?s high performance cmos technology. synchr onous features with data strobe allow extremely high performance up to 6.4gb/ s/chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, and programmable latencies allow the devi ce to be useful for a variet y of high performance memory system applications. for 2m x 32bit x 8 bank gddr3 sdram - 5 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b pin configuration normal package (top view) vddq vdd vss zq vssq dq0 dq1 vssq vddq dq2 dq3 vddq vssq wdqs0 rdqs0 vssq vddq dq4 dm0 vddq vdd dq6 dq5 cas vss vssq dq7 ba0 vref a1 ras cke vssa rfu1 rfu2 vddq vdda a10 a2 a0 vss vssq dq25 a11 vdd dq24 dq27 a3 vddq dq26 dm3 vddq vssq wdqs3 rdqs3 vssq vddq dq28 dq29 vddq vssq dq30 dq31 vssq vddq vdd vss sen mf vss vdd vddq vssq dq9 dq8 vssq vddq dq11 dq10 vddq vssq rdqs1 wdqs1 vssq vddq dm1 dq12 vddq cs dq13 dq14 vdd ba1 dq15 vssq vss we a5 vref vddq ck ck vssa a4 a6 a8/ap vdda a7 dq17 vssq vss a9 dq19 dq16 vdd vddq dm2 dq18 vddq vssq rdqs2 wdqs2 vssq vddq dq21 dq20 vddq vssq dq23 dq22 vssq reset vss vdd vddq 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m n p r t v ba2 note : 1. rfu1 is reserved for future use 2. rfu2 is reserved for future use - 6 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. cmd, add inputs are sampled on the crossing of the posi- tive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). ck and ck should be maintained stable except self-refresh mode. cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buff- ers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power- down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selec- tion on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm0 ~dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write a ccess. dm is sampled on bot h edges of clock. although dm pins are input only, the dm l oading matches the dq and wdqs loading. ba0 ~ ba2 input bank address inputs: ba0, ba1 and ba2 define to which bank an active, read, write or precharge com- mand is being applied. a0 ~ a11 input address inputs: provided the row address for active co mmands and the column address and auto pre- charge bit for read/write commands to select one location out of the memory array in the respective bank. a8 is sampled during a precharge command to deter mine whether the precharge applies to one bank (a8 low) or all banks (a8 high). if only one bank is to be precharged, the bank is selected by ba0, ba1,ba2. the address inputs also provide the op- code during mode register set commands. row addresses : ra0 ~ ra11, column addresses : ca0 ~ ca7, ca9 . column address ca8 is used for auto precharge. dq0 ~ dq31 input/ output data input/ output: bi-directional data bus. rdqs0 ~ rdqs3 output read data strobe: output with read data. rdqs is edge-aligned with read data. wdqs0 ~ wdqs3 input write data strobe: input with write data. wdqs is center-aligned to the inout data. nc/rfu no connect: no internal electrical connection is present. v ddq supply dq power supply v ssq supply dq ground v dd supply power supply v ss supply ground v dda supply dll power supply v ssa supply dll ground v ref supply reference voltage: 0.7*vddq , 2 pins : (h12) for data input , (h1) for cmd and address mf input mirror function for clamshell m ounting of drams. vddq cmos input. zq reference resistor connection pin for on-die termination. res input reset pin: reset pin is a vddq cmos input sen input scan enable : must tie to the ground in case not in use. vddq cmos input. - 7 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b mirror function the gddr3 sdram provides a mirror f unction (mf) ball to change the physical lo cation of the control lines and all address li nes which helps to route dev ices back to back. the mf ball will affect ras , cas , we , cs and cke on balls h3, f5, h9, f9 and h4 respectively and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a 11, ba0, ba1 and ba2 on balls k4, h2, k3, m4, k9, h11, k10, l9, k11, m9, k2, l4, g4, g9 and h10 respectively and only detects a dc input. the mf ball should be tied directly to vss or vdd dependin g on the control line orientation desired. when the mf ball is tied low the ba ll orientation is as follows, ras - h3, cas - f4, we - h9, cs - f9, cke - h4, a0 - k4, a1 - h2, a2 - k3, a3 - m4, a4 - k9, a5 - h11, a6 - k10, a7 - l9, a8 - k11, a9 - m9, a10 - k2, a11 - l4 , ba0 - g4, ba1 - g9 and ba2 - h10. the high condition on the mf bal l will change the location of the control balls as follows; cs - f4, cas - f9, ras - h10, we - h4, cke - h9, a0 - k9, a1 - h11, a2 - k10, a3 - m9, a4 - k4, a5 - h2, a6 - k3, a7 - l4, a8 - k2, a9 - m4, a10 - k11, a11 - l9, ba0 - g9, ba1 - g4 and ba2 - h3. mirror function signal mapping pin mf logic state high low ras h10 h3 cas f9 f4 we h4 h9 cs f4 f9 cke h9 h4 a0 k9 k4 a1 h11 h2 a2 k10 k3 a3 m9 m4 a4 k4 k9 a5 h2 h11 a6 k3 k10 a7 l4 l9 a8 k2 k11 a9 m4 m9 a10 k11 k2 a11 l9 l4 ba0 g9 g4 ba1 g4 g9 ba2 h3 h10 - 8 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b block diagram (2mbit x 32i/o x 8 bank) * ick : internal clock bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 2m x 32 sense amp 4-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ick addr lcke ick cke cs ras cas we dmi ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr 128 32 32 lwe ldmi x32 dqi input buffer 128 output dll input buffer rdqs wdqs 2m x 32 2m x 32 2m x 32 2m x 32 2m x 32 2m x 32 2m x 32 - 9 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge functional description simplified state diagram write - 10 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b initialization gddr3 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. 1. apply power and keep cke/reset at low state ( all other inputs may be undefined) - apply vdd and vddq simultaneously - apply vddq before vref. ( i nputs are not recognized as valid until after v ref is applied ) 2. required minimum 100us for the stabl e power before reset pin transition to high - upon power-up the address/command active terminat ion value will automatically be se t based off the state of reset and cke. - on the rising edge of reset the cke pin is latched to determine the address an d command bus termination value. if cke is sampled at a zero the address termination is set to 1/2 of zq. if cke is sampled at a one the address termination is set to zq. - reset must be maintained at a logic low level and cs at a logic high value during powe r-up to ensure that the dq outp uts will be in a high-z state, all active terminators off, and all dlls off. 4. minimum 200us delay required prior to appl ying any executable command after stable power and clock. 5. once the 200us delay has been satisfied, a deselect or nop command should be applied, then reset and cke should be brought to high, 6. issue a precharge all command following after nop command. 7. issue a emrs command (ba1ba0="01") to enable the dll. 8. issue mrs command (ba0ba1 = "00") to re set the dll and to program the operating parameters. 20k clock cycles are required between the dll to lock. 9. issue a precharge all command 10 . issue at least two auto refresh command to updat e the driver impedance and calibrate the output drivers. following these requirements, the gddr 3 sdram is ready for normal operation. code v dd v ddq v ref ck ck res cke cke command dm a0-a7, a9-a11 a8 ba0, ba1 rdqs wdqs dq ra code ra code bao=h, ba nop pre lmr lmr pre ar ar act high high high ba1 =l bao=l, ba1 =l t=10ns power-up: v dd and ck stable t = 200us trp tmrd trfc trp trfc load extended mode register tmrd 20k load mode register t is t ih code t is t ih t is t ih t is t ih t is t ih t is t ih t0 t1 ta0 tb0 tc0 td0 te0 tf0 t at s t ath t ch t cl t is t ih precharge all banks precharge all banks 1st auto refresh 2nd auto refresh dll reset all banks all banks - 11 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 0 the mode register stores the data for controlling the various operating modes of gddr3 sdram. it programs cas latency, addressing mode, test mode and various vendor spec ific options to make gddr3 s dram useful for variety of dif- ferent applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for the proper operation. the mode register is written by asserting low on cs , ras , cas and we (the gddr3 sdram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 , ba 2 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum clock cycles specified as tmrd are required to comp lete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycl e requirements during operation as long as all banks are in the idle state. the mode register is di vided into various fields depending on functionality. the burst length uses a 0 ~ a 1 . cas latency (read latency from column address) uses a 2 , a 6 ~ a 4 . a 7 is used for test mode. a 8 is used for dll reset. a 9 ~ a 11 are used for write latency. refer to the table for specific codes for various addressing modes and cas latencies. mode register set(mrs) cas latency a 2 a 6 a 5 a 4 cas latency 0000 8 0001 9 0010 10 0011 11 0100 4 0101 5 0110 6 0111 7 1 0 0 0 reserved(12) 1 0 0 1 reserved(13) 1 0 1 0 reserved(14) 1 0 1 1 reserved(15) 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved ba 2 ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 test mode a 7 mode 0normal 1test burst type a 3 burst type 0 sequential 1 reserved dll a 8 dll reset 0no 1yes rfu 0 0 wl dll tm cas latency bt cl burst length burst length a 1 a 0 burst length 00 reserved 01 reserved 10 4 11 8 ba 1 ba 0 a n ~ a 0 00 mrs 01emrs write latency a 11 a 10 a 9 write latency 000 reserved 001 1 010 2 011 3 100 4 101 5 110 6 111 7 note : dll reset is self-clearing rfu(reserved for future use) should stay "0" during mrs cycle - 12 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 0 burst length read and write accesses to the gddr3 sdra m are burst oriented, with the burst l ength being programmable, as shown in mrs table. the burst length determines the maxi mum number of column locations that can be accessed for a given read or write com- mand. reserved states should not be used, as unknown operation or incompatibility wi th future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectiv ely selected. all accesses for that burst take place within the block, meaning that the burst will wrap within t he block if a boundary is reached. the block is uniquely selected by a2-a i when the burst length is set to four (where a i is the most significant column address bit fo r a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmable burst length appli es to both read and write bursts. burst type accesses within a given burst must be progr ammed to be sequential; this is referred to as the burst type and is selected via bi t m3. this device does not support the interleaved burst mode found in ddr sdram devices . the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in below table: burst definition note : 1. for a burst length of four, a2-a7 select the block of four burst; a0-a1 select the starting column within the block and must be set to zero 2. for a burst length of eight, a3-a7 select the block of eight burst; a0-a2 select the starting column within th e block. programmable impedance output buffer and active terminator the gddr3 sdram is equipped with programmabl e impedance output buffers and active terminat ors. this allows a user to match the driver impedance to the system. to adjus t the impedance, an external precision resi stor(rq) is connect ed between the zq pin and vss. the value of the resistor must be six times of the desired output impedance. for example, a 240 ? resistor is required for an output impedance of 40 ? . to ensure that output impedanc e is one sixth the value of rq (within 10 %), the range of rq is 120 ? to 360 ? (20 ? to 60 ? ) output impedance. mf,sen, res, ck and /ck are not internally terminated. ck and /ck will be terminated on the s ystem module using external 1% resisters. the output impedance is updated during all auto refresh commands and nop commands when a read is not in progress to compensate for variations in voltage supply and tem perature. the output impedance upda tes are transparent to the sy stem. impedance updates do not affect device operati on, and all data sheet timing and current s pecifications are met during update. t o guar- antee optimum output driver impedance after pow er-up, the gddr3(x32) needs at least 20us after the clock is applied and stable to cal- ibrate the impedance upon power-up. the user may operate the part with less than 20us , but the optimal out put impedance is not guaranteed. the value of zq is also used to calibrated the inte rnal address/command termination re sisters. the two termination values that are selectable during power up are 1/2 of zq and zq. the value of zq is used to calibrate the internal dq termination resi sters. the two termination values that are sele ctable are 1/4 of zq and 1/2 of zq. burst definition burst length starting column address order of accesses within a burst type= sequential 4 a2 a1 a0 0 0 0 0 - 1 - 2 - 3 8 a2 a1 a0 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 - 13 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 0 cas latency (read latency) the cas latency is the delay, in clock cycles, between the regi stration of a read command and the availability of the first bi t of output data. the latency can be set to 4~11 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . below table indicates the operating fr equencies at which each cas latency set- ting can be used. reserved states should not be used as unknown operation or incompatib ility with future versions may result. cas latency allowable operating frequency (mhz speed cl=11 cl=10 cl=9 cl=8 cl=7 -12 800---- -14 700--- -16 600 - - -20 - 500 nop nop nop read t0 t5 t7 t7n /ck ck command t6 rdqs dq cl = 7 nop nop nop read t0 t6 t8 t8n /ck ck command t7 rdqs dq cl = 8 burst length = 4 in the cases shown shown with nominal t ac and nominal t dsdq don?t care transitioning data - 14 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b write latency the write latency (wl) is the delay, in clock cycles, between the registration of a write command and the availability of the first bit of input data. the latency can be set from 1 to 7 clocks depending in the operating fr equency and desired current draw. when the w rite latencies are set to 1 or 2 or 3 clocks, the input receivers nev er turn off when the write comm and is registered. if a write co mmand is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . reserved states should not be used as unknown operation or in compatibility with future versions may result. nop nop nop write t0 t1 t3 t3n /ck ck command t2 dq wl = 3 nop nop nop write t0 t2 t4 t4n /ck ck command t3 dq wl = 4 burst length = 4 in the cases shown don?t care transitioning data wdqs wdqs - 15 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 0 test mode the normal operating mode is selected by issuing a mode regist er set command with bits a7 set to zero, and bits a0-a6 and a8- a11 set to the desired values. test mode is entered by issuing a mo de register set command with bit a7 set to one, and bits a0- a6 and a8-a11 set to the desired values. test mode functions ar e specific to each dram manufac turer and its exact functions are hidden from the user. dll reset the normal operating mode is selected by issuing a mode regist er set command with bit a7 set to zero, and bits a0-a6 and a8- a11 set to the desired values. a dll reset is initiated by issuing a mode register set command with bit a8 set to one, and bits a0- a7 and a9-a11 set to the desired values. when a dll reset is comple te the gddr3 sdram reset bit 8 of the mode register to a zer o. after dll reset mrs, power down can not be issued within 10 clock. in case the clock frequency need to be changed after the power-up, 512mb gddr3 doesn?t require dll reset. instead, dll shou ld be disabled first before the frequency changed and then change the clock frequency as needed. afte r the clock frequency changed , there needed some time till clock become stable and then enable the dll and then 20k cycle required to lock the dll clock frequency change sequence after the power-up(example) command wait until ck,ck 700mbps 1000mbps emrs dll disable clock stable emrs dll enable 20k cycle for dll locking time ~ ~ ~ ~ ~ ~ ~ ~ any command - 16 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b the extended mode register stores the data output driver strength and on-die termination options. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0(the gddr3 sdram should be in all bank precharge with cke already high prior to writing into the extended mode regis- ter). the state of address pins a0 ~ a11 and ba0,ba1,ba2 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. the minimum clock cycles specified as tmrd are required to complete the write operation in the extended mode register. 4 kinds of the output driver strength are sup- ported by emrs (a1, a0) code. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. "high" on ba0 is used for emrs. refer to the table for specific codes. extended mode register set(emrs) ba 2 ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dll a 6 dll 0 enable 1 disable additive latency a 8 al 00 11 rfu 0 1 term id ron al twr dll twr termination driver strength ba 1 ba 0 a n ~ a 0 00 mrs 01emrs addr/cmd termination a 11 termination 0 default 1 half of deafult vendor id a 10 vendor id 0off 1on twr a 7 a 5 a 4 twr 000 11 001 13 010 5 011 6 100 7 101 8 110 9 111 10 drive strength a 1 a 0 driver strength 00 autocal 01 30 ? 10 40 ? 11 50 ? data termination a 3 a 2 termination 00 odt disabled *1 01 reserved 10 zq/4 11 zq/2 * zq : resistor connection pin for on-die termination rfu(reserved for future use) should stay "0" during emrs cycle * 1 : all odt will be disabled default value is determined by cke status at the rising edge of reset during power-up ron of pull-up a 9 ron 0 40 ? 160 ? - 17 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 0 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after disabling the dll for debugging or evaluation. (when the device exits self refresh mode, the dll is enabled automatically.) any time th e dll is enabled, 20k clock cycles must occur before a read command can be issued. data termination the data termination, dt, is used to determine the value of the internal data termination resisters. the gddr3 sdram supports 60 ? and 120 ? termination. the termination may also be disabled for testing and other purposes. data driver impedance the data driver impedance (dz) is used to determine the value of the data drivers impedance. when autocalibration is used the data driver impedance is set to 40 ? s and it?s tolerance is determined by the calibration accuracy of the device. when any other value is selected the target impedance is set nominally to the desired impedance. however, the accuracy is now determined by the device?s specific proce ss corner, applied voltage and operating temperature. additive latency the additive latency function (al) is used to optimize the command bus efficiency. the al value is used to determine the number of clock cycles that is to be added to cl after cas is captured by the ri sing edge of ck. thus the total cas latency is determined by adding cl and al. manufacturers vendor code an d revision identification the manufacturers vendor code, v, is selected by issuing a extended mode register set command with bits a10 set to one, and bits a0-a9 and a11 set to the desired values. when the v function is enabled the gddr3 sdram will pro- vide its manufacturers vendor code on dq[3:0 ] and revision identi fication on dq[7:4] manufacturer dq[3:0] reserved 0 samsung 1 infineon 2 elpida 3 etron 4 nanya 5 manufacturer dq[3:0] hynix 6 mosel 7 winbond 8 esmt 9 reserved a reserved b manufacturer dq[3:0] reserved c reserved d reserved e micron f - 18 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b vendor id read don?t care transitioning data t0 t1 tb3 tc4 td5 ck ck te 6 ta 2 tf7 res cke cke command dq[3:0] t is t ih t ch t cl t is t ih high vendor code >20ns >20ns 200 cycle t rp t mrd t mrd t mrd t rp precharge all banks emrs vendor_id on mrs 1st auto refresh precharge all banks emrs vendor_id off ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ emrs emrs mrs pre - 19 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b clock frequency chan ge sequence during the device operation nop nop nop nop nop nop pre mrs pre nop ar nop tfchg trp frequency change all banks precharge dll reset tmrd all banks precharge 20tck (dll locking time) ck ck cmd both existing tck and desired tck are in dll-on mode - change frequency from existing frequency to desired frequency - issue precharge all banks command - issue mrs command to reset the dll while other fields are valid and required 20k tck to lock the dll - issue precharge all banks command . issue at least auto-refresh command existing tck is in dll-on mode wh ile desired tck is in dll-off mode - issue precharge all banks command - issue emrs command to disable the dll - issue precharge all banks command - change the frequency from existing to desired. - issue auto-refresh comm and at least two. issue mrs command emrs pre pre nop nop nop ar mrs nop nop nop nop tfchg frequency change ck ck cmd trp all banks precharge dll off tmrd all banks precharge clock frequency change in case existing tck is in dll-off mode while desired tck is in dll-on mode - issue precharge all banks command and issue emrs command to disable the dll. - issue precharge all banks command. - change the clock frequency from existing to desired - issue precharge all banks command. - issue emrs command to enable the dll - issue mrs command to reset the dl l and required 20k tck to lock the dll. - issue precharge all banks command. - issue auto-refresh command at least two emrs pre pre nop nop nop pre emrs mrs pre nop ar tfchg trp frequency change all banks precharge dll on tmrd all banks precharge 20tck (dll locking time) ck ck cmd dll reset tmrd trp all banks precharge dll off tmrd all banks precharge - 20 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b boundary scan function figure 1. internal block diagram (reference only) pins under test ck d dq dm0 tie to iogic 0 ck d dq dqs ck d dq dq4 ck d dq rdqs0 res (ssh,scan shift) cs# (sck, scan clock) mf (soe#, output enable) rfu at v-4 (sen, scan enable) wdqs0 (sout,scan out) puts device into scan mode and re-maps pins to scan functionality dedicated scan flops (1per signal under test) the following lists the rest of the signals on the scan chain: dq[3:0], dq[31:6], rdqs[3:1], wdqs[3:1], dm[3:1], rfu, cas#, we#, cke, ba[2:0], a[11:0], ck, ck# and zq two rfu?s(i-2 and j-3 on 136-ball package) will be on the scan chain and will read as a logic "0" the following lists signals not on the scan chain: nc, vdd, vss, vddq, vssq, vref in case zq pin is connected to the external resistor, it will be read as logic "0". however, if the zq pin is open, it will be read as floating. accordingly, zq pin should be driven by any signal. general information the 512mb gddr3 incorporates a modified boundary scan test m ode as an optional feature. this mode doesn?t operate in accor- dance with ieee standard 1149.1 - 1990. to save the current gd dr3 ball-out, this mode will scan parallel data input and outpu t and the scanned data through wdqs0 pin controlled by an add-on pi n, sen which is located at v-4 of 136 ball package. for the normal device operation other than boundary scan, there r equired device re-initialization by device power-off and then power-on. disabling the scan feature it is possible to operate the 512mb gddr3 without using the boundar y scan feature. sen(at v-4 of 136 ball package) should be tied low(vss) to prevent the device from enter ing the boundary scan mode. the other pins which are used for scan mode, res, mf, wdqs0 and cs# will be operating at normal gd dr3 functionalities when sen is deasserted. - 21 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b boundary scan exit order *note : 1. when the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. since the other input of the mux for dm0 tied to gnd, the device will output the condinuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. two rfu balls(#57and #58) in the scan order, will be read as a logic"0". scan pin description *note : 1. when sen is asserted, no commands are to be executed by the gddr3. this applies to both user commands and manufacturing com mands which may exist while res is deasserted. 2. all scan functionalities are valid only after the appropriate power-up and initialization sequesnce. (res and cke, to set th e odt of the c/a) 3. in scan mode, the odt for the address and control lines set to a nominal termination value of zq. the odt for dq?s will be d isabled. it is not necessary for the termination to be calibrated. 4. in a double-load clam-shell configuration, sen will be asserted to both devices. separate two soe ?s should be provided to top and bottem devices to access the scanned output. when either of the devices is in scan mode, soe for the other device which not in a scan will be disabled. bit# ball bit# ball bit# ball bit# ball bit# ball bit# ball 1 d-3 13 e-10 25 k-11 37 r-10 49 l-3 61 g-4 2 c-2 14 f-10 26 k-10 38 t-11 50 m-2 62 f-4 3 c-3 15 e-11 27 k-9 39 t-10 51 m-4 63 f-2 4 b-2 16 g-10 28 m-9 40 t-3 52 k-4 64 g-3 5 b-3 17 f-11 29 m-11 41 t-2 53 k-3 65 e-2 6 a-4 18 g-9 30 l-10 42 r-3 54 k-2 66 f-3 7 b-10 19 h-9 31 n-11 43 r-2 55 l-4 67 e-3 8 b-11 20 h-10 32 m-10 44 p-3 56 j-3 9 c-10 21 h-11 33 n-10 45 p-2 57 j-2 10 c-11 22 j-11 34 p-11 46 n-3 58 h-2 11 d-10 23 j-10 35 p-10 47 m-3 59 h-3 12 d-11 24 l-9 36 r-11 48 n-2 60 h-4 package ball symbol normal function type description v-9 ssh res input scan shift. capture the data input from the pad at logic low and shift the data on the chain at logic high. f-9 sck cs input scan clock. not a true clock, could be a single pulse or series of pulses. all scan inputs will be referenced to rising edge of the scan clock. d-2 sout wdqs0 output scan output. v-4 sen rfu input scan enable. logic high would enable the device in to scan mode and will be disabled at logic low. must be tied to gnd when not in use. a-9 soe mf input scan output enable. enables (registered low) and disables (registered high) sout data. this pin will be tied to vdd or gnd through a resistor (tyically 1k ? ) for nor- mal operation. tester needs to overdr ive this pin gurarantee the required input logic level in scan mode. - 22 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b scan dc electrical characteristics and operating conditions *note : 1. the parameter applies only when sen is asserted. 2. all voltages referenced to gnd. parameter/conditon symbol min max units notes input high (logic 1) voltage v ih (dc) v ref +0.15 - v 1,2 input low (logic 0) voltage v il (dc) - v ref -0.15 v 1,2 tses tscs tsds tsds valid low sck sen ssh soe pins under test sck sen ssh soe sout tses tscs tscs scan out bit 0 scan out bit 1 scan out bit 2 scan out bit 3 tsac tsoh figure 2. scan capture timing figure 3.scan shift timing not a true clock, but a single pulse or series of pulses don?t care transitioning data - 23 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b scan ac electrical characteristics *note : 1. the parameter applies only when sen is asserted. 2. scan enable should be issued earlier than other scan commands by 3ns. parameter/conditon symbol min max units notes clock clock cycle time tsck 40 - ns 1 scan command time scan enable setup time tses 20 - ns 1,2 scan enable hold time tseh 20 - ns 1 scan command setup time for ssh, soe# and sout tscs 14 - ns 1 scan command hold time for ssh, soe# and sout tsch 14 - ns 1 scan capture time scan capture setup time tsds 10 - ns 1 scan capture hold time tsch 10 - ns 1 scan shift time scan clock to valid scan output tsac - 6 ns 1 scan clock to scan output hold tsoh 1.5 - ns 1 tats tats tscs tsch tscs tsch tsds tsdh valid tsds tsdh valid tses tsds tsdh valid tscs t = 200us reset at power - up boundary scan mode scan out bit0 tscs vdd vddq vref res (ssh in scan mode) cke (dual-load c/a) cke (quad-load c/a) sen sck soe# sout pins under test note : to set the pre-defined odt for c/a, a boundary scan m ode should be issued after an appropriate odt initialization seque nce with res and cke signals figure 4. scan initialization sequence - 24 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b truth table - commands truth table - dm operation name (function) cs ras cas we addr notes deselect (nop) h x x x x 8, 11 no operation (nop) l h h h x 8 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (ent er self refresh mode) l l l h x 6, 7 load mode register l l l l op-code 2 data terminator disable x h l h x name (function) dm dqs notes write enable l valid write inhibit h x 10 1. cke is high for all commands except self refresh. 2. ba0~ba1 select either the mode register or the ex tended mode register (ba0=0, ba1 =0 select the mode register; ba0=1, ba1=0 select extended mode register; other comb inations of ba0~ba1 are reserved). a0~a11 provide the op-code to be written to the selected mode register. 3. ba0~ba2 provide bank address and a0~a11 provide row address. 4. ba0~ba2 provide bank address; a0~a7 and a9 provide co lumn address; a8 high enabl es the auto precharge feature (nonpersistent) , and a8 low disables the auto precharge feature. 5. a8 low : ba0~ba2 determine which bank is precharged. a8 high : all banks are precharged and ba0~ba2 are "don?t care." 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressi ng; ll inputs and i/os are "don?t care" except for cke. 8. deselect and nop are functionally interchangeable. 9. cannot be in powerdown or self-refresh state. 10. used to mask write data ; provided coincident with the corresponding data. 11. except data termination disable. note : commands below truth table-commands provides a quick reference of available commands. this is followed by a verbal descrip- tion of each command. two additional truth tables appear following the operation section : these tables provide current state/next state information. - 25 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 0 deselect the deselect function (/cs high) prevents new command s from being executed by t he ddr(x32). the gddr3(x32) sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is us ed to instruct selected gddr3(x32) to perform a nop (/cs low). this pre- vents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a0-a11. see mode r egister descriptions in the register definition section. the load mode register command can only be issued when all banks are idle, and a subsequent executable command can- not be issued until tmrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0,ba1, ba2 inputs selects the bank, and the address provided on inputsa0-a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharg e command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1, ba2 inputs selects the bank, and the address provided on inputs a0-a7, a9 selects the starting column location. the value on input a8 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be pre- charged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write ,v the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1, ba2 inputs selects the bank, and the address provided on inputs a0-a7, a9 selects the starting column location. the value on inputs a8 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be pre- charged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low. the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one banks are to be pre- charged, inputs ba0,ba1,ba2 select the ba nk. otherwise ba0, ba1,ba2 are treated as "don?t care." once a bank has been precharged, it is in the idle state and must be activa ted prior to any read or write command will be treated as a nop if there is no open row is already in the process of precharging. - 26 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b auto precharge auto precharge is a feature which performs the same indi vidual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a8 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is auto- matically performed upon completion of the read or write burs t. auto precharge is nonpersis tent in that it is either enable or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid state within a burst. this "earliest valid stage" is determined as if an explicit precharge command was issued at the earliest possible time, without violating t ras(min) , as described for each burst type in the operation sec- tion of this data sheet. the user must not issue anot her command to the same bank until the precharge time(t rp ) is com- pleted. auto refresh auto refresh is used during normal operation of the gddr3 sdram and is analogous to /cas-before-/ras (cbr) refresh in fpm/edo drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don?t care" during an auto refresh command. the 512mb(x32) gddr3 requires auto refresh cycles at an average interval of 3.9us (maximum). a maximum auto refresh commands can be posted to any given gddr3(x32) sdram, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 x 3.9us(35.1us). this maximum absolute interval is to allow gddr3(x32) sdram out put drivers and internal termina tors to automatically recali- brate compensating for voltage and temperature changes. self refresh the self refresh command can be used to retain data in the gddr3(x32) sdra m ,even if the rest of the system is powered down. when in the self refresh mode,the gddr3(x32) sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automati- cally disabled upon entering self refresh and is automatically enabled and reset upon exiting self refresh. the active termination is also disabled upon en tering self refresh and en abled upon exiting self re fresh. (20k clock cycles must then occur before a read comma nd can be issued). input signals except cke are "don?t care" during self refresh. the procedure for exiting self refresh requires a sequence of commands. first, ck and /ck must be stable prior to cke going back high. once cke is high,the gd dr3(x32) must have nop commands issued for txsnr because tine is required for the completion of any internal refr esh in progress. a simple algorithm for meeting both refresh, dll requirements and out-put ca libration is to apply nops for 20k clock cycles before applying any other command to allow the dll to lock and the output drivers to recalibrate. data terminator disable (bus snooping for read command) the data terminator disable command is detected by the device by sn ooping the bus for read commands excluding /cs. the gddr3 dram will disable its data termi nators when a read command is detected. the terminators are disable cl-1 clocks after the read co mmand is detected. in a two rank system both dram devices will snoop the bus for read commands to either device and both will disable their terminators if a read command is detected. the com- mand and address terminators and always enabled. - 27 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b on-die termination bus snooping for read commands other than /cs is used to c ontrol the on-die termination in the dual load configuration. the gddr3 sdram will disable the on-die termination when a read command is detected, regardless of the state of /cs, when the odt for the dq pins are set for dual loads (120 ?). the on-die termination is di sabled x clocks after the read command where x equals cl-1 and stay off for a duration of bl/2 + 2, as below figure, data termination disable timing. in a two-rank system, both dram devices snoop the bus fo r read commands to either device and both will dis- able the on-die termination if a read command is detected. the on-die termination for all other pins on the device are always on for both a single-rank system and a dual-rank system. the on-die termination value on address and control pins is dete rmined during power-up in relation to the state of cke on the first transition of reset. on the rising edge of reset, if cke is sampled low, then the configuration is determined to be a single-rank system. the on-d ie termination is then set to one-half zq for t he address pins. on th e rising edge of reset, if cke is sampled high, then th e configuration is determined to be a d ual-rank system. the on-die termination for the dqs, wdqs, and dm pi ns is set in the emrs. nop nop nop nop nop read t0 t7 t8 t8n t9 t9n t10 t11 ck# ck command address rdqs dq bank a, col n cl = 8 do n dq termination gddr3 data termination is disabled data termination disable timing note : 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out appear in the specified order following do n . 4. shown with nominal t ac and t dqsq . 5. rdqs will start driv ing high one-half cycle prior to the first falling edge. 6. the data terminators are disabled starting at cl-1 and the duration is bl/2 + 2 7. reads to either rank disable bot h ranks? termination regardles s of the logic level of /cs. don?t care transitioning data - 28 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b operations bank/row activation before any read or write commands can be issued to a banks within the gddr3 sdram, a row in that bank must be "opened." this is accomplished via the active command, which selects both the bank and the row to be activated. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command in which a r ead or write command can be entered. for example, a t rcd specification of 16ns wit h a 800mhz clock (1.25ns period) results in 12.8 clocks rounded to 13. this is reflected in below figure, which covers any case where 12 - 30 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b t0 t1 t2 t2n t3 t3n t4 ck# ck rdqs 1.6 dq(last data valid) dq(first data no longer valid) all dqs and rdqs, collectively 5 t ch t dqsq 2 (max) t ch t2 t2n t3 t3n t2 t2n t3 t3n t2 t2n t3 t3n t dqsq 2 (min) t dqsq 2 (max) t dqsq 2 (min) t dqsh 4 t dqsh 4 t dv 4 t dv 4 t dv 4 t dv 4 data output timing (1) - t dqsq , t qh and data valid window data output timing (2) - t dqsq , t qh and data valid window t0 t1 t2 t2n t3 t3n t4 ck# ck rdqs 1.6 all dqs and rdqs, collectively 5 t2 t2n t3 t3n t dqsh 4 t dqsh 4 t2 t2n t3 t3n t ac (max) t dqsh 4 t dqsh 4 t ac (min) all dqs and rdqs, collectively 5 rdqs 1.6 t ch t ch note : 1. t dqsq represents the skew between the 8 dq lines and the respective rdqs pin. 2. t dqsq is derived at each rdqs clock edge and is not cumulative over time and begins with first dq transition and ends with the last valid transition of dqs. 3. t ac is show in the nominal case 4. t dqhp is the lesser of tdqsl or tdqsh strobe transition collec tively when a bank is active. 5. the data valid window is derived for each rdqs transitions and is defined by t dv . 6. there are 4 rdqs pins for this device with rdqs0 in relation to dq0-dq7, rdqs1 in relation dq8-dq15, rdqs2 in relation to dq16-24 and rdqs3 in relation to dq25-dq31. 7. this diagram only represents one of the four byte lanes. 8. t ac represents the relationship between dq, rdqs to the crossing of ck and /ck. - 31 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b nop nop nop nop nop read t0 t7 t8 t9 t9n t10 t11 /ck ck command address rdqs dq bank a, col n cl = 9 do n 1. do n =data-out from column n . 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. shown with nominal t ac and t dqsq. 5. rdqs will start driving high 1/2 cl ock cycle prior to the first falling edge. note : don?t care transitioning data read burst nop nop nop nop nop read t0 t7 t8 t8n t9 t9n t10 t11 /ck ck command address rdqs dq bank a, col n cl = 8 do n - 32 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b consecutive read bursts nop read nop nop nop read t0 t7 t8 t8n t9 t10 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t9n do b 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. three subsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cy cle prior to the first falling edge of rdqs. note : don?t care transitioning data t2 - 33 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b nonconsecutive read bursts don?t care transitioning data nop nop nop read nop read t0 t7 t8 t8n t9 t9n t10 t17 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, col b t17n t18 nop do b nop nop nop read nop read t0 t1 t7 t8 t8n t9 t10 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t11 nop do b 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. three subpsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. example applies when read comm ands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. note : - 34 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b random read accesses don?t care transitioning data note : nop nop nop nop nop read t0 t1 t2 t8 t8n t9 t10 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t9n do b do n do n do n nop nop read nop nop read t0 t1 t7 t8 t8n t9 t10 /ck ck rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t9n do b do n do n do n command address 1. do n (or x or b or g ) = data-out from column n (or column x or column x or column b or column g ). 2. burst length = 4 3. n ? or x or b ? or g ? indicates the next data-out following do n or do x or do b or do g , respectively 4. reads are to an active row in any bank. 5. shown with nominal t ac and t dqsq. 6. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. - 35 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b read to write don?t care transitioning data note : 1. do n = data-out from column n . 2. di b = data-in from column b . 3. burst length = 4 4. one subsequent element of data-out appears in the programmed order following do n . 5. data-in elements are applied following di b in the programmed order. 6. shown with nominal t ac and t dqsq. 7. t dqss in nominal case. 8. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. 9. the gap between data termination enable to t he first data-in should be greater than 1tck nop nop write nop nop read t0 t7 t8 t9 t9n t10 t11 /ck ck command address rdqs dq bank col n cl = 8 dm t8n do n di b t wl = 4 wdqs dq nop t12 t12n bank a, col b 1tck < termination dq termination disabled dq termination enbaled - 36 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b read to precharge don?t care transitioning data note : nop nop pre nop act read t0 t1 t2 t8 t8n t9 t10 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, (a or all) t9n bank a, row t rp nop nop pre nop act read t0 t1 t7 t8 t8n t9 t10 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, (a or all) bank a, row t rp 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n. 4. three subsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. example applies when read comm ands are issued to different de vices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cy cle prior to the first falling edge of rdqs. - 37 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b writes write bursts are initiated with a write command, as shown in figure. the starting column and bank addresses are provided with the write command, and auto precharge is ei ther enabled or disabled for that access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered in a rising edge of wdqs following the write latency set in the mode register and subsequent data elements will be registered on successive edges of wdqs. prior to the first valid wdqs edge a half cycle is needed and spec- ified as the write preamb le; the half cycle in wd qs following the last data-in element is known as the write postamble. the time between the write command and the first valid falling edge of wdqs (t dqss ) is specified with a relative to the write latency. all of the write diagrams show the nominal case, and where the two extreme cases (i.e., t dqss(min) and t dqss(max) ) might not be intuit ive, they have also been included. write burst figure shows the nominal case and the extremes of tdqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored. data for any write burst may not be truncated with a subsequent write command. the new write com- mand can be issued on any positive edge of clock following the previous write command after the burst has completed. the new write com- mand should be issued x cycles after the first write command should be equals the number of desired nibbles (n ibbles are required by 4n-prefetch architecture). an example of nonconsecutive writes is shown in nonconsecutive write to read figure. full-speed random write accesses within a page or pages can be performed as shown in random write cycl es figure. data for any write burst may be followed by a subsequent read command. data for any write burst may be followed by a subsequent pre- charge command. to follow a write the write burst, t wr should be met as shown in writ e to precharge figure. data for any write burst can not be truncated by a subsequent pre- charge command. /ck ck ca en ap dis ap ba /cs /ras /cas /we a0-a7, a9 a10, a11 a8 ba0,1,2 cke high write command ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge don?t care - 38 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b nop nop nop nop nop write t0 t1 t2 t3 t3n t4 t5 /ck ck command address bank a, col b t dqss nop t4n t5n t6 dq dm di b wdqs di b di b t dqss (nom) dq dm wdqs t dqss (min) dq dm wdqs t dqss (max) t dqss t dqss write burst don?t care transitioning data note : 1. di b = data-in for column b. 2. three subsequent elements of data-in are appl ied in the programmed order following di b. 3. a burst of 4 is shown. 4. a8 is low with the write co mmand (auto precharge is disabled). 5. write latency is set to 4 - 39 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b consecutive write to write don?t care transitioning data note : nop nop write nop nop write t0 t1 t3 t3n t4 t5 ck# ck command address bank col b t dqss (nom) nop t4n t5n t6 dq dm wdqs t2 t6n t7 nop di b di n bank col n 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are app lied in the programmed order following di b . 3. three subsequent elements of data-in are app lied in the programmed order following di n . 4. burst of 4 is shown. 5. each write command may be to any bank of the same device. 6. write latency is set to 3 - 40 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b nonconsecutive write to write don?t care nop nop nop write nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank, col b nop t4n t5n t6 dq dm di b wdqs t2 t6n t7 nop di n bank, col n t dqss (nom) don?t care transitioning data note : 1. di b, etc. = data-in for column b, etc. 2. three subsequent elements of data-in are app lied in the programmed order following di b. 3. three subsequent elements of data-in are app lied in the programmed order following di n. 4. burst of 4 is shown. 5. each write command may be to any bank. 6. write latency is set to 3 - 41 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b random write cycles don?t care transitioning data note : nop write nop nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank col b t dqss (nom) nop t4n t5n t6 dq dm wdqs t2 t6n t7 nop di b di x bank col x write bank col g di b di b di b di x di x di x di g di g 1. di b, etc. = data- in for column b, etc. 2. b: etc. = the next data - in following di b. etc., accordi ng to the programmed burst order. 3. programmed burst length = 4 cases shown. 4. each write command may be to any bank. 5. last write command will have the rest of the nibble on t8 and t8n 6. write latency is set to 3 - 42 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b write to read don?t care transitioning data note : nop nop write nop nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank col b t dqss nop t4n t6 dq dm wdqs t2 t10 read di b bank col b t18 t19 nop nop t dqss (nom) bank a. col n cl = 8 rdqs t dqss dq dm wdqs di b di n t dqss (min) cl = 8 rdqs di n t dqss dq dm wdqs di b di n t dqss (max) cl = 8 rdqs tcdlr = 5 t19n 1. di b = data-in for column b . 2. three subsequent elements of data-in the programmed order following di b. 3. a burst of 4 is shown. 4. t cdlr is referenced from the first positive ck edge after the last data-in pair. 5. the read and write commands are to the same device. however, t he read and write commands may be to different devices, in which case t cdlr is not required and the read command could be applied earlier. 6. a8 is low with the write command (auto precharge is disabled). 7. write latency is set to 3 - 43 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b write to precharge don?t care transitioning data note : nop nop write nop nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank col b t dqss nop t4n t8 dq dm wdqs t2 t9 pre di b bank col b t10 t11 nop nop t dqss (nom) bank (a or all) t dqss dq dm wdqs di b t dqss (min) t dqss dq dm wdqs di b t dqss (max) t wr t rp 1. di b = data-in for column b . 2. three subsequent elements of data- in the programmed order following di b . 3. a burst of 4 is shown. 4. a8 is low with the write command (auto precharge is disabled). 5. write latency is set to 3 - 44 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time (t rp ) after the pre- charge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1, ba2 select the bank. when all banks are to be precharged, inputs ba0, ba1, ba2 are treated as "don?t care." once a bank has been precharged, it is in the idle state and must be acti- vated prior to any read or write commands being issued to the bank. power-down (cke not active) unlike sdr sdrams,gddr3(x32) sdram requires cke to be active at all times an access is in progress; from the issuing of a read or write command until completion of the burst. for reads, a burst com- pletion is defined when the read postamble is satisfied; for writes, a burst completion is define d bl/2 cycles after the write postamble is sat- isfied. power-down is entered when cke is registered low. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and out- put buffers, excluding ck,/ck and cke. for maximum power savings, the user has the option of disabling the dll prior to entering power- down. however, power-down duration is limited by the refresh require- ments of the device, so in most appl ications,the self-refresh mode is pre- ferred over the dll-disabled power-down mode. when in power-down, cke low and a stable clock signal must be maintained at the inputs of the gddr3 sdram, while all other input sig- nals are "don?t care" except data terminator disable command. the power-down state is synchronously exited when cke is registered high (in conjunct ion with a nop or deselec t command). a valid exe- cutable command may be applied tpdex later. all banks one bank ba /cs /ras /cas /we a0-a7, a9-a11 ba0,1,2 ba=bank address /ck ck cke high a8 don?t care (if a8 is low; otherwise "don?t care") precharge command nop nop nop valid t0 t1 ta0 ta1 ta2 /ck ck command valid ta 7 t2 cke t is t pdex t is no pead/write access in progress * enter power - down mode exit power - down mode power-down * once the device enters the pow er down mode, it should be in nop state at least for 10ns - 45 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b gddr3 tfaw definition for eight bank gddr3 devices, there is a need to limit the nu mber of activates in a rolling window to ensure that the instanteous current supplying capability of the devices is not exceeded. to reflect the true capability of the dram instanta- neous current supply, the same parameter tfaw(four activate window) as ddr2 is defined. eight bank device sequential bank activation restriction : no more than 4 banks may be activated in a rolling tfaw win- dow. converting to clocks is done by di viding tfaw(ns) by tck(ns) and rounding up to next integer value. as an example of the rolling window, if (tfaw/tc k) rounds up to 10 clocks, and an activate command is issu ed in clock n, no more than three further activate co mmands may be issued in clocks n+1 through n+9. t rrd clk act t rrd t rrd t rrd t rrd t rrd cmd t faw t faw + 3*t rrd act act act act act act act - 46 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b truth table - clock enable (cke) notes : 1. cken is the logic state of cke at clock edge n ; cken-1was the state of cke at the previous clock edge. 2. current state is the state of the ddr2(x32) immediately prior to clock edge n . 3. commandn is the command registered at clock edge n , and action n is a result of command n 4. all state and sequence not shown are illegal or reserved. 5. deselect or nop commands sh ould be issued on any clock edges o ccurring during the t xsa period. cken-1 cken current state commandn actionn notes ll power-down x maintain power-down self refresh x maintain self refresh lh power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 5 hl all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry - 47 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b truth table - cu rrent state bank n - command to bank n notes : 1. this table applies when cke n-1 was high and cke n is high (see cke truth table) and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (i.e., t he current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). exceptions ar e covered in the notes below. 3. current state definitions : idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read : a read burst has been initiated, with auto precharge disabled. write : a write burst has been initiated, with auto precharge disabled. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are det ermined by its current state and truth table- current state bank n command to bank n . and according to truth table - current state bank n -command to bank m. precharging : starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating : starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the :row active" state. current state /cs /ras /cas /we command/ action notes any h x x x deselect (nop/ continue previous operation) l h h h no operation (nop/continue previous operation) x h l h data terminator disable idle l l h h active (select and activate row) l l l h auto refresh 7 row active llllload mode register 7 l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto-precharge disable) l h l h read (select column and start new read burst) 10 l h l l write (select column and start write burst) 10, 12 l l h l precharge (only after t he read burst is complete) 8 write (auto-precharge disabled) l h l h read (select column and start read burst) 10, 11 l h l l write (select column and start new write burst) 10 l l h l precharge (only after the write burst is complete) 8, 11 - 48 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b read w/ auto- : starts with registration of an read command with auto precharge enabled and ends precharge enabled when trp has been met. once t rp is met, the bank will be in the idle state. write w/ auto- : starts with registration of a write command with auto precharge enabled and ends precharge enabled when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command ; co mmand inhibit or nop commands must be applied on each positive clock edge during these states. refreshing : starts with regi stration of an auto refresh command and ends when t rc is met. once t rc is met, the ddr2(x32) will be in the all banks idle state. accessing mode : starts with regi stration of a load mode register command and ends when t mrd has been met. once t mrd is met, the gddr3(x32) sdram will be in the all banks idle state. precharge all : starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. read or write : starts with registration of the active command and ends the last valid data nibble. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. may or may not be bank-specific ; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. left blank 10. reads or writes listed in the co mmand/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking. 12. a write command may be applied after the completion of the read burst. - 49 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b truth table - curr ent state bank n - command to bank m notes : 1. this table applies when cke n-1 was high and cke n is high (see truth table- cke ) and after t xsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, exce pt where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. current state /cs /ras /cas /we command/ action notes any h x x x deselect (nop/ continue previous operation) l h h h no operation (nop/continue previous operation) x h l h data terminator disable idle xxxxany comm and otherwise allowed to bank m row activating, active, or prechrging l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge read (auto-precharge disable) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge write (auto-precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 6, 7 l h l l write (select column and start new write burst) 6 l l h l precharge read (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge write (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start new write burst) 6 l l h l precharge - 50 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b 3. current state definitions : idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regi ster accesses are in progress. read : a read burst has been initiated, with auto precharge disabled. write : a write burst has been initiated, with auto precharge disabled. read w/ auto- precharg e enabled : see following text write w/ auto- precharg e enabled : see following text 3a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts : the access period and the precharge period . for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible pre- charge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr command and ends where the precharge period (or t rp ) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read and write commands to the other bank ma y be applied. in either case, all other related limitations apply (e.g., contention between read data write data must be avoided). 3b. the minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized below. 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. all states and sequences not shown are illegal or reserved. 6. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 7. requires appropriate dm masking. from command to command minimum delay (with concurrent auto precharge) write w/ap read or read w/ap [wl + (bl/2)] tck + twr write or write w/ap (bl/2) * tck precharge 1 tck active 1 tck read w/ap read or read w/ap (bl/2) * tck write or write w/ap [cl ru + (bl/2)] + 1 - wl * tck precharge 1 tck active 1 tck - 51 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b stresses greater than those listed under "absolute maximum ra tings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other c onditions above those indicated in the operat ional sections of this specificat ion is not implied. exposure periods may affect reliability. note : power & dc operating conditions recommended operating conditions (voltage referenced to 0 c tc 85 c) note : 1.under all conditions, vddq must be less than or equal to vdd. 3. vref is expected to equal 70% of vddq for the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed + 2 percent of the dc value. thus, fr om 70% of vddq, vref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 4. the dc values define where the input slew rate requirements are imposed, and the input signal must not violate the se levels in order to maintain a valid level. the inputs require the ac value to be achieved during signal transition edge and the driver shoul d achieve the same slew rate through the ac values. 5. input and output slew rate =3v/ns. if the input slew rate is less than 3v/ns, input timing may be compromised. all slew rate are measured between vih and vil. dq and dm input slew rate must not deviate from dqs by more than 10%. if the dq,dm and dqs slew rate is less than 3v/ns, timing is longer than referenced to the mid-point but to the vil(ac) maximum and vih(ac) minimum points. 6. vih overshoot : vih(max) = vddq + 0.5v for a pulse width 500ps and the pulse width can not be greater than 1/3 of the cycle rate. vil undershoot : vil(min)=0.0v for a pulse width 500ps and the pulse width can not be greater than 1/3 of the cycle rate. 7. K4J52324QC-bj** 8. K4J52324QC-bc** parameter symbol min typ max unit note device supply voltage v dd 1.9 2.0 2.1 v 1,7 output supply voltage v ddq 1.9 2.0 2.1 v 1,7 device supply voltage v dd 1.7 1.8 1.9 v 1,8 output supply voltage v ddq 1.7 1.8 1.9 v 1,8 reference voltage v ref 0.69*v ddq - 0.71*v ddq v3 dc input logic high voltage v ih (dc) v ref +0.15 - - v 4 dc input logic low voltage v il (dc) --v ref -0.15 v 4 output logic low voltage v ol(dc) - - 0.76 v ac input logic high voltage v ih(ac) v ref +0.25 - - v 4,5,6 ac input logic low voltage v il(ac) --v ref -0.25 v 4,5,6 input leakage current any input 0v- - 53 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b dc characteristics-i note : 1. measured with outputs open and odt off 2. refresh period is 32ms parameter symbol test condition version unit -bj12 -bj14 operating current (one bank active) i cc1 burst length=4 t rc t rc (min) i ol =0ma, t cc = t cc (min) 510 490 ma precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 120 110 ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min) 270 240 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 140 130 ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) 420 400 ma operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks activated. 1075 980 ma refresh current i cc5 t rc t rfc 525 500 ma self refresh current i cc6 cke 0.2v 50 50 ma operating current (4bank interleaving) i cc7 burst length=4 t rc t rc (min) i ol =0ma, t cc = t cc (min) 1195 1100 ma parameter symbol test condition version unit -bc14 -bc16 -bc20 operating current (one bank active) i cc1 burst length=4 t rc t rc (min) i ol =0ma, t cc = t cc (min) 420 410 400 ma precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 90 85 80 ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min) 200 190 170 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 110 100 95 ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) 320 315 310 ma operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks activated. 830 760 655 ma refresh current i cc5 t rc t rfc 480 460 440 ma self refresh current i cc6 cke 0.2v 50 50 50 ma operating current (4bank interleaving) i cc7 burst length=4 t rc t rc (min) i ol =0ma, t cc = t cc (min) 935 860 830 ma ( 0 c tc 85 c ; vdd=2.0v + 0.1v, vddq=2.0v + 0.1v ) dc characteristics-ii ( 0 c tc 85 c ; vdd=1.8v + 0.1v, vddq=1.8v + 0.1v ) - 54 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b ac characteristics (i-i) note : 1. the write latency can be set from 1 to 7 clocks. when the write latency is set to 1 or 2 or 3 clocks, the input buffe rs are turned on during the active commands reducing the latency but a dded power. when the write latency is set to 4 ~7 clocks which must b e greater than 7ns, the input buffers are turned on during the write commands for lower power operation. 2. a low to high transition on the wdqs line is not allowed in the half clock prior to the write preamble. 3. the last rising edge of wdqs after the write postamble must be riven high by the controller. wdqs can not be pull ed high by the on-die termination alone. 4. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are no t referenced to a specific voltage level, but specify when t he device output is no longer driving (hz) or begins driving (lz). 5. the cycle to cycle jitter over 1~6 cycle short term jitter parameter sym- bol -bj12 -bj14 unit note min max min max dqs out access time from ck t dqsck -0.23 +0.23 -0.26 +0.26 ns ck high-level width t ch 0.45 0.55 0.45 0.55 tck ck low-level width t cl 0.45 0.55 0.45 0.55 tck ck cycle time cl=11 t ck 1.25 3.3 3.3 ns cl=10 1.4 1.4 ns cl=9 1.6 1.6 ns cl=8 2.0 2.0 ns cl=7 2.0 2.0 ns write latency t wl 6-5-tck1 dq and dm input hold time relative to dqs t dh 0.16 - 0.18 - ns dq and dm input setup time relative to dqs t ds 0.16 - 0.18 - ns active termination setup time t ats 10 - 10 - ns active termination hold time t ath 10 - 10 - ns dqs input high pulse width t dqsh 0.48 0.52 0.48 0.52 tck dqs input low pulse widthl t dqsl 0.48 0.52 0.48 0.52 tck data strobe edge to dout edge t dqsq -0.140 0.140 -0.160 0.160 ns dqs read preamble t rpre 0.4 0.6 0.4 0.6 tck dqs read postamble t rpst 0.4 0.6 0.4 0.6 tck write command to first dqs latching transition t dqss wl-0.2 wl+0.2 wl-0.2 wl+0.2 tck dqs write preamble t wpre 0.35 - 0.4 0.6 tck 2 dqs write preamble setup time t wpres 0-0-ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 tck 3 half strobe period t hp tclmin or tchmin - tclmin or tchmin - tck data output hold time from dqs t qh t hp -0.14 - t hp -0.16 -ns data-out high-impedance window from ck and /ck t hz -0.3 - -0.3 - ns 4 data-out low-impedance window from ck and /ck t lz -0.3 - -0.3 - ns 4 address and control input hold time t ih 0.3 - 0.35 - ns address and control input setup time t is 0.3 - 0.35 - ns address and control input pulse width t ipw 0.9 - 1.0 - ns jitter over 1~6 clock cycle error tj - 0.03 - 0.03 tck 5 cycle to cyde duty cycle error tdcerr - 0.03 - 0.03 tck rise and fall times of ck tr, tf - 0.2 - 0.2 tck - 55 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b ac characteristics (i-ii) note : 1. the write latency can be set from 1 to 7 clocks. when the write latency is set to 1 or 2 or 3 clocks, the input buffe rs are turned on during the active commands reducing the latency but a dded power. when the write latency is set to 4 ~7 clocks which must b e greater than 7ns, the input buffers are turned on during the write commands for lower power operation. 2. a low to high transition on the wdqs line is not allowed in the half clock prior to the write preamble. 3. the last rising edge of wdqs after the write postamble must be riven high by the controller. wdqs can not be pull ed high by the on-die termination alone. 4. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are no t referenced to a specific voltage level, but specify when t he device output is no longer driving (hz) or begins driving (lz). 5. the cycle to cycle jitter over 1~6 cycle short term jitter parameter sym- bol -bc14 -bc16 -bc20 unit note min max min max min max dqs out access time from ck t dqsck -0.26 +0.26 -0.29 +0.29 -0.35 +0.35 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 tck ck cycle time cl=11 t ck 3.3 - 3.3 - 3.3 ns cl=10 1.4 ns cl=9 1.6 1.6 - ns cl=8 2.0 2.0 - ns cl=7 2.0 2.0 2.0 ns write latency t wl 5-5-4-tck1 dq and dm input hold time relative to dqs t dh 0.18 - 0.20 - 0.25 - ns dq and dm input setup time relative to dqs t ds 0.18 - 0.20 - 0.25 - ns active termination setup time t ats 10 - 10 - 10 - ns active termination hold time t ath 10 - 10 - 10 - ns dqs input high pulse width t dqsh 0.48 0.52 0.48 0.52 0.48 0.52 tck dqs input low pulse widthl t dqsl 0.48 0.52 0.48 0.52 0.48 0.52 tck data strobe edge to dout edge t dqsq -0.160 0.160 0.180 0.180 0.225 0.225 ns dqs read preamble t rpre 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 tck write command to first dqs latching transition t dqss wl-0.2 wl+0.2 wl-0.2 wl+0.2 wl-0.2 wl+0.2 tck dqs write preamble t wpre 0.4 0.6 0.4 0.6 0.4 0.6 tck 2 dqs write preamble setup time t wpres 0-0-0-ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 3 half strobe period t hp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tck data output hold time from dqs t qh t hp -0.16 - t hp -0.18 - t hp -0.225 -ns data-out high-impedance window from ck and /ck t hz -0.3 - -0.3 - -0.3 - ns 4 data-out low-impedance window from ck and /ck t lz -0.3 - -0.3 - -0.3 - ns 4 address and control input hold time t ih 0.35 - 0.4 - 0.5 - ns address and control input setup time t is 0.35 - 0.4 - 0.5 - ns address and control input pulse width t ipw 1.0 - 1.1 - 1.3 - ns jitter over 1~6 clock cycle error tj - 0.03 - 0.03 - 0.03 tck 5 cycle to cyde duty cycle error tdcerr - 0.03 - 0.03 - 0.03 tck rise and fall times of ck tr, tf - 0.2 - 0.2 - 0.2 tck - 56 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b ac characteristics ii-i parameter symbol -bj12 -bj14 unit note min max min max row active time t ras 25 100k 22 100k tck row cycle time t rc 35 - 31 - tck refresh row cycle time t rfc 45 - 39 - tck ras to cas delay for read t rcdr 12 - 10 - tck ras to cas delay for write t rcdw 8-6-tck row precharge time t rp 10 - 9 - tck row active to row active t rrd 8-8-tck four activate window t faw 40 - 40 - tck last data in to row precharge (pre or auto-pre) t wr 11 - 10 - tck last data in to read command t cdlr 6-5-tck mode register set cycle time t mrd 7-6-tck auto precharge write recovery time + precharge t dal 21 - 19 - tck exit self refresh to read command t xsr 20000 - 20000 - tck power-down exit time t pdex 7tck +tis - 6tck +tis -tck refresh interval time t ref - 3.9 - 3.9 us ac characteristics ii-ii parameter symbol -bc14 -bc16 -bc20 unit note min max min max min max row active time t ras 22 100k 19 100k 15 100k tck row cycle time t rc 31 - 28 - 22 -tck refresh row cycle time t rfc 39 - 33 - 27 - tck ras to cas delay for read t rcdr 10 - 10 - 8 -tck ras to cas delay for write t rcdw 6- 6 - 5 -tck row precharge time t rp 9- 9 - 7 -tck row active to row active t rrd 8-7-5 tck four activate window t faw 40 - 35 - 25 - tck last data in to row precharge (pre or auto-pre) t wr 10 - 9 - 7 - tck last data in to read command t cdlr 5-4-3-tck mode register set cycle time t mrd 6-5-4-tck auto precharge write recovery time + precharge t dal 19 - 18 - 14 -tck exit self refresh to read command t xsr 20000 - 20000 - 20000 - tck power-down exit time t pdex 6tck +tis - 6tck +tis - 4tck +tis -tck refresh interval time t ref -3.9-3.9-3.9us - 57 - rev 1.0 (mar 2005) 512m gddr3 sdram K4J52324QC-b package dimensions (fbga) 14.0 11.0 0.35 0.05 1.20 max |
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